1. Field of the Invention
This invention relates generally to data processing systems and more particularly to the exchange of logic signals on a system bus in the data processing system. As techniques have been found to increase the performance of the main memory system, increased transfer of data over the system bus is necessary to utilize the enhanced main memory capability.
2. Description of the Related Art
Referring to FIG. 1, a typical data processing system configuration is shown. The data processing system includes at least one central processing unit 10 (or 11), at least one input/output unit 13 (or 14), a memory unit 15 and a system bus 19 coupling the plurality of units (or subsystems) of the data processing system. The central processing unit processes groups of logic signals according to software and/or firmware instructions. The logic signal groups to be processed as well as the program instruction sequences can typically be stored in the memory unit 15. A console unit 12 can be coupled to the central processing unit(s) and includes the apparatus and stored instructions to initialize the system. The console unit can be used as a terminal during the operation of the data processing system. The input/output units provide the interface between the data processing system and terminal units, mass storage units, communication units, and any other units to be coupled to the data processing system.
Referring next to FIG. 2, a block diagram of a typical main memory system found in the related art is shown. The main memory unit 15 includes a memory interface unit 21 that exchanges signals with the system bus 19. The memory interface unit 21 is coupled to an array bus 22 and the memory unit bus 22 has at least one memory array unit 26 coupled thereto. The memory array units are comprised of a plurality of logic signal storage elements organized in groups so that each group of storage elements can be accessed by a unique address logic signal group. The memory interface unit 21 includes the apparatus for controlling the exchange of logic signal groups, identified by an address logic signal group, between the memory arrays and the system bus. The memory interface unit 21 includes apparatus for identifying activity on system bus 19 directed to the memory unit as well as apparatus for returning logic signal groups to the subsystems transmitting requests for the signal groups. Buffering of the data signal groups, error correction and generation of control signal are also typically performed in the memory interface unit 21.
The use of the system bus in a data processing system provides flexibility by allowing a variable number of subsystems to be coupled to the system bus and therefore a multiplicity of configurations are possible. However, the exchange of signal groups between the data processing subsystems is constrained to take place on the system bus. A protocol is typically established that permits each data processing subsystem to have access to the system bus in a manner that permits the interaction between requisite subsystems while avoiding conflicts between the subsystems. The protocol can severely limit the bus activity. In addition, as the number of subsystems coupled to the system bus increases, the access to the system bus can be a limiting factor in the performance of the data processing system. The problem is especially severe in the "write through" data processing systems where all the data signal groups generated by the central processing unit are stored into the main memory.
The exchange of data signal groups between a central processing unit and a main memory unit can be classified into three groups; write operations in which signal groups from the central processing unit are stored in the main memory unit, read operations in which signal groups are transferred from a main memory unit to a central processing unit, and a read modify write in which signal groups already stored in the main memory unit are partially replaced by signals from a central processing unit. This last operation is typically referred to as a masked write operation, because signals called mask signals that identify the signals of the signal group stored in main memory unit to be replaced are transferred from the central processing system along with the signals to be stored. As is well known, the masked write operation is more time consuming than the read or write operation. Associated with each operation is a command that is transferred to the main memory subsystem to notify the main memory subsystem of the type of action required. In particular, the masked write command causes the apparatus of the main memory unit to be responsive to the mask signals and begin a read operation of the data signal group to be merged with the incoming data signal group.
In order to increase the system bus usage, multiple write commands, command that transfer a plurality of consecutively addresse signal groups to be written (stored) to the main memory on consecutive system clock cycles, can be employed. This procedure can improve the system bus utilization. However, many situations can arise where the multiple write procedure is not applicable, such as when a system need write only three data signal groups in a sequence of four. System bus utilization could be improved if a procedure similar to the multiple write operation could be used in the transfer of partially filled sequential signal groups, the improvement being a result of the reduction in the number of system clock cycles that are not directly uesed for signal group transfer.
A need has therefore been felt for apparatus and method for increasing the efficiency of data signal group exchange on the data processing system bus by transferring multiple signal groups in which at least one of the groups in the multiple groups is not to be stored. In addition, a need was felt to perform the multiple group transfer (with missing signal groups) while minimizing additional apparatus to implement the transfer.